Optimization of semiconductor devices continues to be an important goal for the semiconductor industry. The continued miniaturization of semiconductor devices, such as bipolar transistors, presents ongoing challenges to semiconductor manufacturers in maintaining or improving that optimization while maintaining product yields and minimizing production time and costs. One such challenge resides in reducing the writer leakage associated with bipolar transistors, such as NPN bipolar transistors.
As performance requirements have continued to increase, writer leakage concerns have become more important to semiconductor manufacturers and attention has begun to be focused on how to decrease writer leakage. For example, in a specific device, writer leakage can occur when a circuit cannot maintain a specific voltage (˜300 mV) across the write head when a current of 50 uA is injected through the head. When this occurs, the write head open circuit does not function properly, and operating voltages cannot be maintained at required levels for optimum device performance when writer leakage occurs. As a result, device yield and performance is decreased, and as device sizes continue to shrink and performance requirements continues to increase, writer leakage will have even a greater impact.
Accordingly, there is a need to provide a process and device by which writer leakage is reduced in a bipolar transistor device.